1. Field of the Invention
The prevent nvention relates to either discrete devices or integrated power semiconductor devices including MOS-gated power devices such as, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices. In particular, the invention relates to a MOS-gated power device having a smaller minimum dimension Lp that yields an increased density of MOS-gated power devices per unit area.
2. Discussion of the Related Art
MOS technology power devices as known in the related art are composed of a plurality of elementary functional units integrated in a semiconductor chip. Each elementary functional unit is a vertical MOSFET, and all the elementary functional units are connected in parallel. With this arrangement, each elementary vertical MOSFET contributes a fraction of an overall current capacity of the power device.
A MOS technology power device chip typically includes a lightly doped semiconductor layer of a first conductivity type forming a common drain layer for all the elementary vertical MOSFETS. The lightly doped layer is superimposed over a heavily doped semiconductor substrate. Each elementary functional unit includes a body region of a second conductivity type formed in the common drain layer. U.S. Pat. No. 4,593,302 (Lidow et al.) discloses a so called "cellular" power device, wherein the body region of the elementary functional units has a polygonal layout, such as for example a square or hexagonal shape. For this reason, the elementary functional units are also called "elementary cells". In addition, MOS technology power devices are also known in the related art wherein the body region of each elementary functional units is an elongated stripe.
For any of the above power MOS devices, a typical vertical structure of the elementary functional units (i.e. a cross-section view) of the MOS technology power device is as shown in FIG. 1. In FIG. 1, the heavily doped semiconductor substrate is indicated by reference numeral 1 and the lightly doped semiconductor layer is indicated by reference numeral 2. The body region 3 of the elementary functional unit includes a central heavily doped portion 4, called a "deep body region", and a lateral lightly doped portion 5, having a lower dopant concentration than the heavily doped deep body region, which forms a channel region of the elementary vertical MOSFET. A doping level of the lateral portions 5 of the body region determines a threshold voltage of the power device. Inside the body region 3, a source region 6 of the same conductivity type as the common drain layer 2 is formed. A thin oxide layer 7 (a gate oxide layer) and a polysilicon layer 8 (a gate electrode of the power device) cover a surface of the semiconductor layer 2 between the body regions 3, and the layers also extend over the lightly doped lateral portion of the body regions. The polysilicon layer 8 is covered by a dielectric layer 9 in which contact windows 11 are opened over each body region to allow a superimposed metal layer 10 (a source electrode of the power device) to be deposited through the contact window and to contact the source regions 6 and the deep body region 4.
In the structure of FIG. 1, a short-circuit is defined between the source region and the deep body region to prevent a parasitic bipolar junction transistor having an emitter, a base and a collector respectively formed by the source region 6, the deep body region 4 and the heavily doped semiconductor substrate 1, from triggering on. The parasitic bipolar transistor will trigger "on" if the lateral current flow in the body below the source produces a voltage drop greater than approximately 0.7 V, forward biasing the emitter-to-base (EB) junction. The deep body region 4 increases the ruggedness of the power device because it reduces the base resistance of such a parasitic transistor.
The structure of FIG. 1 is manufactured by forming the common drain layer 2 over the heavily doped substrate 1, generally by means of an epitaxial growth. The thin oxide layer 7 is thermally grown over an active area of the common drain layer 2, wherein the elementary functional units of the MOS-gated power device will be formed, and the polysilicon layer 8 is deposited on the thin oxide layer. The deep body regions 4 are formed by selective introduction via a mask of a high dose of a dopant to form the central heavily doped deep body regions 4. Windows 12 are formed in the gate oxide layer and the polysilicon layer by a selective etching of the polysilicon and gate oxide layers via a second mask to open the windows 12 where the elementary functional units will be formed. The lateral lightly doped portions of the body regions are then formed by selective introduction of a low dose of dopants into the common drain layer through the windows to form the lightly doped portions of the body regions. Next, the source regions 6 are formed as will be described in more detail below, followed by deposition of the dielectric layer 9 and selective etching thereof to open the contact windows 11. The metal layer 10 is then deposited and patterned.
This process involves the use of a minimum of four photolithographic masks: a first mask is used for the formation of the deep body regions 4; a second mask is used to selectively etch the polysilicon 8 and gate oxide 7 layers; a third mask is used to form the source regions 6 and a fourth mask is used to open the contact windows 11 in the dielectric layer 9. The mask for the introduction of the dopants forming the source regions is provided partially by the polysilicon and oxide layers, and partially by photoresist isles over a middle portion of the deep body regions 4. The photoresist isles are formed by depositing a photoresist layer over the common drain layer, selectively exposing the photoresist layer to a light source, and selectively removing the photoresist layer to provide the photoresist isles.
Referring again to FIG. 1, a dimension Lp of each window 12 in the polysilicon 8 and gate oxide 7 layers is given by equation (1): EQU Lp=a+2t (1)
where "a" is the width of the contact window 11 in the dielectric layer 9 and "t" is the distance between an edge of the polysilicon 8 and gate oxide 7 layers and an edge of the window 11 in the dielectric layer 9. The dimension "a" of the contact window is given by equation (2): EQU a=c+2b (2)
where "b" is a distance between an edge of the contact window 11 and an inner edge of the source region 6, or in other words the length of the source region available to be contacted by the metal layer 10, and "c" is the dimension of a surface of the deep body region wherein the source regions are absent or in other words the distance between the inner edges of the source regions, corresponding to the length of the surface of the deep body region available to be contacted by the metal layer. The dimension Lp is therefore given by equation (3): EQU Lp=c+2b+2t (3)
Accordingly, the elementary functional units of the related art have the dimension Lp determined by "three feature sizes", in particular the dimension Lp depends on the parameters "c", "b"and "t".
In MOS technology power devices, the electrical parameters to be optimized are the output resistance in the "on" condition Ron, a gate-to-drain capacitance (feedback capacitance) and a gate-to-source capacitance (input capacitance) of the MOS technology power device for a specific die size and breakdown voltage. The output resistance Ron is the sum of several components, each of which is associated with a particular physical region of the device. More specifically, Ron is made up of the components as shown in equation (4): EQU Ron=Rc+Racc+Rjfet+Repi (4)
where Rc is a channel resistance associated with the channel region, Racc is an accumulation region resistance associated with a surface portion of the common drain layer between the body regions, Rjfet is a resistance associated with a portion of the common drain layer between depletion regions of the body regions 5, and Repi is a resistance associated with a portion of the drain layer beneath the body regions.
The channel resistance Rc depends on process parameters such as the dopant concentration of the channel region. In other words Rc is proportional to the threshold voltage of the MOS technology power device, and to the channel length. The accumulation region resistance Racc depends on the distance "d" between two adjacent body regions, and decreases as such distance decreases. The Rjfet resistance depends on a resistivity of the common drain layer and on the distance "d" between the body regions, and increases as such a distance decreases. The Repi resistance depends on the resistivity and a thickness of the common drain layer, two parameters which also determine a maximum voltage (Bvmax) that can be sustained by the MOS technology power device. Bvmax increases as the resistivity increases, as long as the epi layer is thick enough. The resistivity and the thickness are optimized for the lowest value of Repi. Further, the output resistance Ron is inversely proportional to an overall channel length of the MOS technology power device. In other words Ron is inversely proportional to a sum of the channel of the individual elementary functional units that make up the MOS technology power device. The longer the channel length per unit area of the MOS technology power device, the lower the output resistant Ron per unit area.
Thus, in order to reduce the Ron it is desirable to scale down the dimensions of the elementary functional units and in particular the distance "d" between the body regions as long as Rjfet is not significantly increased, or in other words to increase a density of elementary functional units per unit area. A reduction of the distance "d" between the body regions has a further advantage of lowering the input and feedback capacitances of the MOS technology power device, thus improving its dynamic performance. Also, in high-voltage MOS technology power devices, reducing the distance "d" between the body regions increases the device's ruggedness under switching conditions. A recent technological trend has therefore been toward increasing the density of elementary functional units per unit area, and MOS technology power devices with a density of up to six million elementary cells per square inch can be fabricated.
The structure of the related art however poses some limitations to the further reduction of the dimensions thereof. These limitations are essentially determined by a resolution and alignment characteristics of the photolithographic apparatus used in the process to manufacture the MOS technology power device. Referring again to FIG. 1, it is known that the dimension "c" must be sufficiently large enough to guarantee that the metal layer 10 contacts the body region, and can only be scaled down to the resolution limit of the photolithographic apparatus used to provide the region "c". In addition, the dimension "b" must be sufficiently large enough to guarantee that the metal layer contacts the source region 6, and must also allow for any alignment errors between the mask defining the contact window 11 in the dielectric layer 9 and the mask for the formation of the source regions. Further, the dimension "t" must be sufficiently large enough to guarantee that the polysilicon layer 8 is electrically insulated from the metal layer and must also take into account any alignment errors between the masks for the definition of the windows 12 in the polysilicon layer and the mask for forming the contact windows in the dielectric layer.
In addition, the structure of the elementary functional units according to the related art does not allow reduction of the distance "d" between the elementary functional units below certain values that depend on a voltage rating of the MOS technology power device. For example, the distance "d" is approximately 5 .mu.m for low-voltage devices and in a range from 10 .mu.m to 30 .mu.m for medium- to high-voltage devices. A reduction of the distance "d" below the specified values would in fact cause a rapid increase in the Rjfet component of the Ron of the MOS technology power device, thereby increasing the value of Ron.
In view of the state of the art described, it is an object of the present invention to provide a new MOS technology power device structure which provides an improvement to the MOS technology power devices of the related art.